In research and development this is of course a rather negative way of looking at things and for those of us involved in processing there are many new and exciting challenges. The uncharted territory beyond 100nm will require further developments in lithography, new materials and new processes to cope with the high aspect-ratio smaller geometries. For those involved in front end processing research, the requirements will be for high quality, uniform, defect-free thin films with precision doping and reduced thermal budgets. CMOS compatible solutions will be required and new device structures may well be needed because of limitations imposed by high channel doping levels. DRAM capacitor and gate dielectrics are an area of particular concern as also gate materials themselves and the production and contact to ultra-shallow device junctions. It is probable true to say that no suitable high dielectric constant material with the stability and interface characteristics has yet been identified. Since a physical oxide thickness approaching 1nm is necessary for 100nm geometries, SiO2 cannot be used because of the high tunnelling currents. Will new materials preserve interface state characteristics? Probably not, which means an ultra-thin layer of SiO2, thus imposing a limit on dielectric thickness. The materials constraints are onerous since low electrical leakage is essential and Schottky-Richardson and Fowler-Nordheim tunnelling must be contained as also Poole-Frenkle tunneling. Further, gate electrode material or dopant must not diffuse through and contaminate the channel.
Every aspect of a transistor is of course involved with each step towards larger scale integration and challenges exist for not only for gates but also interconnects, low and high k dielectrics, diffusion barriers, contacts and vias,silicides, souces and drains, retrograde wells, isolation trenches and buried layers, to name some critical functions for CMOS technology.
Public interest tends to focus on memory and ULSI but
this is only one area of advancement in semiconductor device applications.
Research at NISRC is concerned with problems that
affect a wide range of devices, including power applications, bipolar and
analogue circuits, high frequency, and thin film transistor circuits. Some
of the areas of particular interest include metallisation for interconnects,
gate electrodes, diffusion barriers, polysilicon, wafer bonding and
micromachining. Specific technologies would be CVD, PVD,dry and wet etching,
furnace processes, photolithography and wafer bonding methods. Below are
summarised some current research in deposition technologies.
The use of buried metal layers in silicon has advantages for collectors in bipolar transistors and as a ground plane in high frequency circuits. Smart power circuits employing multiple power output devices using dielectric isolation would also benefit from low resistivity buried drains. Silicon wafer fusion bonding is a viable technology for the production of substrates for such applications. In this process the ‘active’ silicon wafer is bonded to an oxidised handle wafer in an ultra clean environment, followed by precision grinding and polishing to reduce the active wafer thickness to the desired value. Metal coating of the active wafer prior to bonding provides a buried metal layer on a dielectrically isolated substrate. Refractory metals allow subsequent high temperature processing and it is convenient to form a silicide, which has adequate conductivity for the required applications, from the buried metal coating during bond annealing. Tungsten silicide is being used in the present work.
A high quality non-voided silicide/silicon interface layer is an essential requirement and the surfaces to be bonded must be free from bow or distortion. Following tungsten deposition a protective cap of polysilicon is deposited by LPCVD which is then polished to a surface finish suitable for bonding to and oxidised handle wafer. For successful bonding it is essential that distortion of the active wafer is not introduced during tungsten deposition and that all particles are removed from the polished polysilicon surface after polishing. The latter process is investigated in the present work using rf magnetron sputtering to deposit tungsten on primary silicon substrate. Previous work (1) had shown that delamination of the silicide/silicon interface can occur after bond-annealing. This was initially attributed to thermal stress, but further investigation had shown that the condition of the primary silicon surface before W deposition was critical and that chemically cleaning treatments had a major effect. The effect of impurities especially oxygen in the formation of silicides is well documented. (2-5). Impurities can in principle originate from primary silicon surface, the bulk, or the W and any subsequent capping layers. It has been suggested that even the naturally occurring thermal oxide layer can impede silicide formation (3). Studies, (2) have shown that substrate heating during W deposition is beneficial to formation of conformal silicide layers although I believe the reasons are not clear cut and require further investigation. Work at NISRC also demonstrates the importance of substrate heating before and during deposition and suggests that its effect may be to drive water-vapour from the surface and hence reduce the contamination level during sputtering. (It was suggested to me recently by G Gawlik that the energy input to the target during sputtering is a critical factor in determining the subsequent integrity of the silicide layer on annealing. The energy of reflected neutrals determines the degree of mixing between depositing atoms and substrate. This seems to me to be the most convincing argument so far and deserves some consideration.)
The current investigation examines the effect of substrate heating during W sputter deposition as a means of ensuring the integrity of the the tungsten silicide/Si boundary layer in bonded wafer structures for buried collectors and other applications. This work was carried out in a standard ‘O’ ring sealed vacuum system suitable for commercial application with fast pump-down and side door (quick-release) opening for loading purposes. No load lock was used but a Class 10 laminar flow hood was mounted over the loading area to minimise particle contamination.
(references to follow)