The NISRC laboratories, located in the Ashby Building of the Queen's University of Belfast, are involved almost exclusively with silicon wafer processing. The research topics below reflect my own interests in deposition technologies particularly with the newer materials being used for electrode and interconnect structures.
The mass market continues to drive semiconductor technology forward, manufacturers demanding from research and development laboratories faster device operation, increased packing densities and more efficient use of power. It is not difficult to imagine the physical and engineering problems raised as microelectronic processing technology moves further into the submicron range. The 1999 SIA roadmap is focussing on the year 2005 for breaking the 100nm barrier, with  the beginning of a new growth phase in the capacity driven market cycle following a period of consolidation there is no lack of incentive to achieve this goal. Even though last year's brick-wall barriers now seem a thing of the past as today's problems are faced,  new predictions are now being made of the eventual limit which physics will surely and finally impose.

In research and development this is of course a rather negative way of looking at things and for those of us involved in processing there are many new and exciting challenges. The uncharted territory beyond 100nm will require further developments in lithography, new materials and new processes to cope with the high aspect-ratio smaller geometries. For those involved in front end processing research, the requirements will be for high quality, uniform, defect-free thin films with precision doping and reduced thermal budgets. CMOS compatible solutions will be required and new device structures may well be needed because of limitations imposed by high channel doping levels. DRAM capacitor and gate dielectrics are an area of particular concern as also gate materials themselves and the production and contact to ultra-shallow device junctions. It is probable true to say that no suitable high dielectric constant material with the stability and interface characteristics has yet been identified. Since a physical oxide thickness approaching 1nm is necessary for 100nm geometries, SiO2 cannot be used because of the high tunnelling currents. Will new materials preserve interface state characteristics? Probably not, which means an ultra-thin layer of SiO2, thus imposing a limit on dielectric thickness. The materials constraints are onerous since low electrical leakage is essential and Schottky-Richardson and Fowler-Nordheim tunnelling must be contained as also Poole-Frenkle tunneling. Further, gate electrode material or dopant must not diffuse through and contaminate the channel.

Every aspect of a transistor is of course involved with each step towards larger scale integration and challenges exist for not only for gates but also interconnects, low and high k dielectrics, diffusion barriers, contacts and vias,silicides, souces and drains, retrograde wells, isolation trenches and buried layers, to name some critical functions for CMOS technology.

Public interest tends to focus on memory and ULSI but this is only one area of advancement in semiconductor device applications. Research at NISRC is concerned with problems that affect a wide range of devices, including power applications, bipolar and analogue circuits, high frequency, and thin film transistor circuits. Some of the areas of particular interest include metallisation for interconnects, gate electrodes, diffusion barriers,  polysilicon, wafer bonding and micromachining. Specific technologies would be CVD, PVD,dry and wet etching, furnace processes, photolithography and wafer bonding methods. Below are summarised some current  research in deposition technologies.

Copper interconnects.

Traditionally, aluminium and since the early seventies, aluminium/copper alloy, has been the preferred material for conductor applications. The material is resistant to corrosion, straightforward to deposit and until the present day has had an acceptable resistivity. The alloying addition of copper has made this material resistant to electromigration as dimensions began to shrink, but with current densities predicted to exceed 10MA/cm2 in the future and todays demand for  faster chip speeds, low resistivity copper is a serious contender and is already being implemented by some manufacturers.
Copper brings its own problems; a poisoner of silicon devices, a strong tendency to corrode in the presence of air, unknown reliability and electromigration behaviour which requires much further research. There are also contact reaction problems and dry etching is difficult because of low reaction temperatures between copper and most contacting material candidates. Corrosion and diffusion into silicon require barrier layers which are discussed below. Current research involves examining alloying elements such as tin, palladium and zirconium to inhibit electromigration without degrading resistivity excessively. PVD and CVD are used for this work.
Resistivity of copper is determined by electron scattering from phonons, impurities, vacancies, dislocations, grain boundaries, precipitated second phase particles and compound phases. Scattering from defects adds linearly to resistivity but vacancies and dislocations can be reduced to an almost negligible level by annealing. Grain boundary scattering is negligible if grains are greater than about 0.3 micron which is normally the case with thin films.Soluble impurities significantly raise the resistivity by roughly 1 microhm-cm per atomic% but will often segregate to grain boundaries and have minimal effect. Second phase and compound phases have much higher resistivities than pure copper and will increase resistivity according their volume fraction and added materials can have unpredictable effects on microstructure with resistivity implications.

Diffusion barrier layers

Copper is a fast diffuser into silicon and can produce deep level defects, hence diffusion barriers are essential. The literature shows that a large number of materials and combinations of materials have been tried, Ti/TiN has been effectively used for this purpose but decreasing device dimensions and the use of copper have intensified the search for improved performance materials, materials that are chemically and thermodynamically stable towards copper migration and diffusion. Examples of promising barrier materials include tantalum, tantalum nitride, tungsten nitride and ternary materials such as tantalum-silicon-nitride and tungsten-silicon-nitride. A newcomer to the scene is tungsten with tantalum, where tungsten-silicide is uniformly produced at the silicon boundary producing stable high temperature performance.


Tungsten is a relatively low resistivity refractory metal and is used in multilevel metallisation and high density interconnect schemes. It is particularly suitable for buried electrode structures used in power devices. It has the further advantage of resistance to electromigration and as stated above, promising for use as a diffusion barrier component. With current technologies conformal coverage is essential and NISRC has been using a CVD process which will deposit within tunnel structures, trenches, and high aspect ratio vias. With PECVD, plasma processes add energy to reactant gases allowing low temperature deposition (<250C). Using WF6 + H2 for example, electron impact leads to sub-fluorides which react with atomic hydrogen (produced in the plasma), at the substrate surface thus creating tungsten and reaction product, HF. Optimum phase and mimimisation of stress in layers can be achieved by careful choice of process conditions (J.Phys.IV France 9 (1999), Pr8 pp.827-833)

Polysilicon deposition

Polycrystalline silicon deposited by a low temperature process is attractive for future production of liquid crystal displays, image scanners and large area electronics.  For flat panel displays for example, direct deposition below the strain point of glass substrates has obvious advantages. Polysilicon has relatively high mobility compared to amorphous silicon and permits fabrication of scanning circuitry, drivers, line storage and decoders around the periphery of active matrix displays. Work at NISRC has shown that high quality crystalline layers can be produced using a PECVD process involving SiF4/SiH4/H2 mixtures. Grain sizes in excess of 90 nm have been obtained for layers deposited at 300C (TSF, 337, (1999), 55-58).

Project example


UNITS: SI including Pascal, 1 Pa = 0.01mbar. (1 Torr  = 133.322  Pa)


The use of buried metal layers in silicon has advantages for collectors in bipolar transistors and as a ground plane in high frequency circuits. Smart power circuits employing multiple power output devices using dielectric isolation would also benefit from low resistivity buried drains. Silicon wafer fusion bonding is a viable technology for the production of substrates for such applications. In this process the ‘active’ silicon wafer is bonded to an oxidised handle wafer in an ultra clean environment, followed by precision grinding and polishing to reduce the active wafer thickness to the desired value. Metal coating of the active wafer prior to bonding provides a buried metal layer on a dielectrically isolated substrate. Refractory metals allow subsequent high temperature processing and it is convenient to form a silicide, which has adequate conductivity for the required applications, from the buried metal coating during bond annealing. Tungsten silicide is being used in the present work.

A high quality non-voided silicide/silicon interface layer is an essential requirement and the surfaces to be bonded must be free from bow or distortion. Following tungsten deposition a protective cap of polysilicon is deposited by LPCVD which is then polished to a surface finish suitable for bonding to and oxidised handle wafer. For successful bonding it is essential that distortion of the active wafer is not introduced during tungsten deposition and that all particles are removed from the polished polysilicon surface after polishing. The latter process is investigated in the present work using rf magnetron sputtering to deposit tungsten on primary silicon substrate. Previous work (1) had shown that delamination of the silicide/silicon interface can occur after bond-annealing. This was initially attributed to thermal stress, but further investigation had shown that the condition of the primary silicon surface before W deposition was critical and that chemically cleaning treatments had a major effect. The effect of impurities especially oxygen in the formation of silicides is well documented. (2-5). Impurities can in principle originate from primary silicon surface, the bulk, or the W and any subsequent capping layers. It has been suggested that even the naturally occurring thermal oxide layer can impede silicide formation (3). Studies, (2) have shown that substrate heating during W deposition is beneficial to formation of conformal silicide layers although I believe the reasons are not clear cut and require further investigation. Work at NISRC also demonstrates the importance of substrate heating before and during deposition and suggests that its effect may be to drive water-vapour from the surface and hence reduce the contamination level during sputtering. (It was suggested to me recently by G Gawlik that the energy input to the target during sputtering is a critical factor in determining the subsequent integrity of the silicide layer on annealing. The energy of  reflected neutrals determines the degree of mixing between depositing atoms and substrate. This seems to me to be the most convincing  argument so far and deserves some consideration.)

The current investigation examines the effect of substrate heating during W sputter deposition as a means of ensuring the integrity of the the tungsten silicide/Si boundary layer in bonded wafer structures for buried collectors and other applications. This work was carried out in a standard ‘O’ ring sealed vacuum system suitable for commercial application with fast pump-down and side door (quick-release) opening for loading purposes. No load lock was used but a Class 10 laminar flow hood was mounted over the loading area to minimise particle contamination.

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